Electronic circuits may remain in one state for long periods of time. For example, during normal operation of the computer system, information may be written to storage circuits (e.g., static random access memory (SRAM)) and seldom, if ever, change. Such conditions can occur both during testing (e.g., voltage stressing) and during actual operation (e.g., storing static information, such as operating system code). As a result of remaining in one state, storage circuits can become stressed (i.e., fatigued).
The stresses on computer chips include negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) of field effect transistors (FETs). In the past, NTBI was considered the dominant contributor to fatigue (e.g., 90% or more). As such, PTBI was discounted in modeling and simulation of circuits. However, PBTI is becoming a substantial contributor to fatigues as the geometry of FETs is scaled ever-smaller.
An n-channel FET (“NFET”) is in a PBTI voltage stress condition when a gate on the NFET is “high” and a source and a drain of the NFET are at a “low” voltage. A p-channel FET (“PFET”) is in an NBTI voltage stress condition when its source and the drain are both at a “high” voltage level and the gate is at a “low” voltage level. NBTI and PBTI cause shifts in the threshold voltages of FETs, which result in performance degradation and voltage sensitivity. For example, marginally functional storage cells of an SRAM may fail due to threshold voltage shifts caused by NBTI and PBTI.